Multi-bit data flip-flops are often used within integrated circuit devices to save power and area in comparison with stand-alone single bit data flip-flops for the same number of bits. For existing multi-bit data flip-flop solutions, every flip-flop bit is typically implemented using a master latch and a slave latch. For some integrated circuit embodiments, multi-bit data flip-flops are also serially connected to provide an internal scan chain. To implement this internal scan chain, each flip-flop bit also typically includes an input multiplexer that selects between a data bit input and a scan bit input. For initialization of each flip-flop bit, additional transistors or control gates are included within the master and slave latches to provide set and reset capabilities. These additional set/reset transistors or gates, however, add to the die area required for the multi-bit data flip-flop circuitry within the integrated circuit device.